What is AXI Lite protocol?
AXI4-Lite is a subset of the AXI4 protocol intended for communication with simpler, smaller control register-style interfaces in components. The key features of the AXI4-Lite interfaces are: All transactions have a burst length of one. All data accesses are the same size as the width of the data bus.
Does AXI Lite support burst?
AXI4-Lite: A subset of AXI, lacking burst access capability. Has a simpler interface than the full AXI4 interface. AXI4-Stream: A fast unidirectional protocol for transfering data from master to slave.
What is the difference between AXI3 and AXI4?
AXI3 supports burst lengths up to 16 beats only. While AXI4 supports burst lengths of up to 256 beats.
What is AXI full form?
The Advanced eXtensible Interface (AXI), is an on-chip communication bus protocol developed by ARM. It is part of the Advanced Microcontroller Bus Architecture 3 (AXI3) and 4 (AXI4) specifications.
Why do we need AXI protocol?
The AXI is a point to point interconnect that designed for high performance, high speed microcontroller systems. The AXI protocol is based on a point to point interconnect to avoid bus sharing and therefore allow higher bandwidth and lower latency. AXI is arguably the most popular of all AMBA interface interconnect.
What is AXI burst length?
AXI3 supports burst lengths of 1 to 16 transfers, for all burst types. AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers. Support for all other burst types in AXI4 remains at 1 to 16 transfers.
What is Awcache in AXI?
The ARCACHE[3:0] or AWCACHE[3:0] signal supports system-level caches by providing the bufferable, cacheable, and allocate attributes of the transaction: Bufferable (B) bit, ARCACHE[0] and AWCACHE[0]
Why is AXI used?
What are the channels in AXI?
In the AXI specification, five channels are described: Read Address channel (AR) Read Data channel (R) Write Address channel (AW)
What is 4KB boundary?
The granularity of mapping in AXI is 4KB. That means the smallest “block” of addresses that can be assigned to a given slave/peripheral is 4K*. And all allocations are multiples of 4K. So when you cross a 4K boundary you are potentially going from slave A’s address space to slave B’s.
What is Bufferable and cacheable?
Bufferable: Write to memory can be carried out by a write buffer while the processor continues on to next instruction execution. Cacheable: Data obtained from memory read can be copied to a memory cache so that next time it is accessed the value can be obtained from the cache to speed up program execution.
What is data interleaving in AXI?
Write data interleaving enables a slave interface to accept interleaved write data with different AWID values. The slave declares a write data interleaving depth that indicates if the interface can accept interleaved write data from sources with different AWID values.